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ASP英文文献翻译2-二号文档

ASP英文文献翻译2

发布时间:2021-10-16 09:53:16

Parallel Microcomputer

Highly versatile, this densely packed parallel processor exploits advanced micre electronic trends.

R . M. Lea Aspex Microsystems Ltd. Brunel University
10

-

ssociative String Processor microcomputers provide highly versatile components for the lowcost implementation of high-performance ,informationprocessing systems. By mapping application data structures to a string representation and supporting content addressing and parallel processing, ASP achieves both application flexibility and a stepfunction improvement in cost-performance figures. This improvement occurs without the loss of computational efficiency usually suffered by general-purpose parallel processors. The ASP architecture offers cost-effective support of a particularly wide range of both numerical and nonnumerical computing applications while exploiting state-of-the-art microelectronic technology. This technology achieves processor packing densities that are more usually associated with memory components. In fact, we designed ASP to benefit from the inevitable VLSI-to-ULSI-to-WSI (very large, ultra large, and wafer-scale integration) technological trend, with a fully integrated, simply scalable, and defect/fault-tolerant processor interconnection strategy. Here, I discuss the architectural philosophy, structural organization, operational principles, and VLSI/ULSI/WSI implementation of ASP and indicate its cost-performance potential. ASP microcomputers have the potential to achieve cost-performance targets in the range of 100 to 1,OOO MOPS/$1,000 (million operations per second). This gives ASPS an advantage of two to three orders of magnitude over current parallel computer architectures. The ASP architecture is based on a fully programmable and reconfigurable, homogeneous computational structure emerging from research at Brunel University and being developed by Aspex Microsystems. offers particularty flexible (see the box on “Associative Processing”) support for structured data processing as indicated by the examples in Table 1. The breadth of this application range indicates a large potential market for ASP within the aerospace, telecommunications, automobile, and manufacturing industries as well as the commercial, defense, and research sectors. It also demonstrates the importance of application flexibility and architectural extensibility (scaling processing power to match application requirements) as ASP design requirements. While ASP exploits the opportunities presented by the latest advances in the VLSI-to-ULSI-to-WSI technological trend, it also makes use of the continually improving highdensity system assembly techniques (multichip,
0272-1732/88/IooM)oIofo1.00 0 1988 IEEE

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Associative Processing
Many information processing applications require users to reference a set of data elements, associated with a common key, by the value of an associated key (rather than by their physical locations within some storage structure). Examples of data elements might include the selection of those Rover cars sold after 1987 with air-conditioning or those graduate software engineers with two years of experience in Ada programming or those pixels corresponding to a particular intensity value in a computer vision system or those facts and rules that are related to a particular query in a knowledge-based artificial intelligence system. With traditional von Neumann computers, such data access requires repeated (sequential)navigation through some tree-structured (possibly complex) indirect-addressing mechanism to unique storage locations (where the sought data may or may not exist). This access method results in loss of accessing efficiency and much redundant processing. In contrast, with associative processing users access the set of data elements in parallel by content addressing and simple association linking. The addresses of such data have no logical significance and only relevant data can be accessed. Moreover, associative processing avoids the additional overheads of sequentiallytransferring data to an external processor by (parallel) in-situ processing. Associative processing involves a particularly flexible and naturally parallel form of symbolic representation and manipulation of structured data (sets, arrays, tables, trees, and graphs) processing. Potential benefits include simplicity of expression, storage capacity, and speed of execution over a wide variety of nonnumerical and numerical information processing applications.

Table 1. ASP information processing applications.

Special-purpose applications Nonnumerical information processing Text processing, database management, office systems, information management Information (document) retrieval for information, legal and patents services Intelligent knowledge-based, or expert, systems (medical, automotive systems) Numerical information processing Digital signal processing in aerospace, military, telecommunications systems Speech recognition in military, business, automotive systems Image-related processing Computerized tomography for medical, industrial, geophysical image reconstruction Image clarification, scene analysis, pattern recognition in support of remote sensing (for satellites and surveillance),artificial vision (for robotics, automation) Computerized image generation for graphic arts and special television effects and CAD/CAM (3D image generation, associated database management) General-purpose applications Vector processing for research modeling and design simulation Symbolic processing for compilation, translation, theorem proving Artificial intelligence processing for fifthgeneration (declarative) support of programming languages such as functional (LISP) and logic-based (Prolog)

multilayer thin-film ceramic, and silicon-on-silicon superhybrids). ASP remains independent of technology, so it can benefit from the inevitable improvement in microelectronics technology without architectural modification.

ported with an ASP data buffer (ADB), a controller, and a data communications network. ASP substrings. Each ASP substring comprises a string of identical APES (associative processing elements), as shown in Figure 2. Each APE connects to an inter-APE communications network (which runs in parallel with the APE string). All APES share common bit-parallel data, activity, and control buses, and one feedback line called Match Reply, or MR. An external controller maintains the buses, feedback line, and Link
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ASP system architecture
As indicated in Figure 1, an ASP system comprises a dynamically reconfigurable parallel processing structure of communicating ASP substrings, each sup-

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ASP
I

I H
interface Data

t

I

Data communications network

ASP
S U

b
S

n

n

t r i n

9

ASP controller

U

1

I

Figure 1. Activation of matching/mismatching APES: before (1) and after (2).

Left and Link Right ports (LKL and LKR) of the interAPE communications network. 24 In contrast to more traditional parallel computer architectures, ASP uses content-matching rather than location-addressing techniques. Thus, ASP selects APES for subsequent parallel processing by comparing their data and activity content with the states of the corresponding data and activity buses. Moreover, the lack of location addressing also simplifies system configuration and extension, implementation, and especially fault tolerance. In operation, each ASP substring supports a form of set processing in which the subset of active APES(those which match broadcast data and activity values) support scalar-vector and vector-vector operations. ASP either directly activates matching APES or uses source inter-APE communications to indirectly activate other APES (see the accompanying box). The match reply line indicates whether or not any APES match. The controller either directly broadcasts scalar data or receives it via the bit-parallel data bus. Similarly, ASP can also exchange input-output vector data (output dumped and input loaded in a single step) sequentiallyin APESvia the data bus with the bitparallel primary data exchanger (PDX). As shown in Figure 2, the bit-parallel primary data exchanger

ADB

- _ .

S
D X

P
Vector data buffer
- D

X

ASP
C 0

n t r
0

I I
e r Data bus Activity bus Control bus

1I I

II I

II

I

II

I

I

PDX =Primary data exchanger LKL =Link left port

LKR =Link right port APE =Associative processing element

Figure 2. ASP substring.
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APE Activation Options
Associative processing elements may be activated for read or write operations by one of the following activation options.

Matching and mismatching APEs
Assuming the state of an ASP substring shown in Figure Al, where M represents matching APEs, acf tivation A o matching and mismatching APEs appears as seen in Figure A2.

Asynchronous communication
For each of the five activation examples shown in Figure B, the first ASP substring state indicates matching M APEs. The second and third states indicate activations A following asynchronous signal transmission (to the left and right respectively) from LKL, LKR, or source S matching APES to destination D previously matched APEs. The examples assume inter-APE communication within a single ASP segment, such that all block links are closed. As an option of the fourth and fifth activations, the first source APE may also be included in the set of activated APEs.

Figure A. Activation of matching/mismatching APES: before (1) and after (2).

Figure B. Activations with asynchronous communication: an isolated matching APE (1); neighbors of matching APES (2); remote APES linked with matching APEs (3); substrings between matching APES (4); and all APES between matching APES and one end of the string (5).

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ASP
PDX Process

(a)
PDX Process SDX

PDX

I
(b)

I

Figure 3. Example of unacceptable loss of efficiency (a); minimal lass of efficiency (b).

Process SDX

I

I

PDX

Similarly, but at a lower data rate, the secondary data exchanger (SDX) provides a bit-parallel vector data exchange between the vector data buffer and the external ADB. The SDX overlaps parallel processing and, therefore, does not present a sequential processing overhead. Consequently, whereas the bit-parallel PDX is a fundamental feature of a substring, the vector data buffer and its support bit-serial PDX and SDX are optional components of ASP. They are incorporated only for those applications requiring relatively short parallel processing periods. Associative processing element. Each APE incorporates an n-bit data register and an a-bit activity register, an @+a)-bit parallel comparator in which the values of n and a are 32 to 128 bits and 4 to 8 bits, depending on the application class for which ASP is optimized. Moreover, an APE includes a single-bit full-adder and four status flags (C to represent arithmetic carry, M and D to tag matching and destination APEs, and A to activate selected APEs). An APE also includes control logic for local processing and communication with other APEs. See Figure 4. Data modes and activity bits. ASP hardware supports three modes of data representation (word, byte, and bit) within the n-bit data register (DR), as defined (in Pascal) in the following example (for n = 32 bits).

exchanges data. However, ASP loses the parallel processing advantage during sequential vector data exchange. Thus, depending on the time required to process the loaded vector data, the exchange could incur an unacceptable loss of parallel processing efficiency, as indicated in Figure 3a. In such cases, a vector data buffer supports a much faster APE-parallel exchange facility, in which a bit-serial PDX performs the task at a very high data rate. Thus we minimize the loss of parallel processing efficiency (Figure 3b).

Inter-APE communications network

Figure 4. Associative processing element, 01 APE.
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DR = record case datamode of wordmode : (word : array bytemode : (byte : array bitmode : (sf-1 : array s f 2 : array sf-3 : array end

Word

I

31

0

1

[0..31] of O..l); [O. .3,0. .7] of 0.. 1); [3..13] of O..l; [14..22] of O..l; [25..31] of O..l)

Byte model

bf-3

I

bf-2

bf-1

bf-0

In word mode the data register provides storage for (and supports bit-parallel processing of) an n-bit binary word, as shown in Figure 5a. Alternatively, in byte mode the data register stores 8-bit byte fields, as shown in Figure 5b, and supports bit-parallel processing of a selected byte field. In bit mode the data register can store variable-length binary fields for bit-serial processing (Figure 5c). Users can declare one, two, or three such serial fields for unary, binary, or ternary bitserial operations. Moreover, data representation is not limited by the n-bits of a single data register, since, in all three data modes, a contiguous string of APES can be allocated for operand storage. In contrast, the a-bit activity register provides storage for an a-element ordered set defined in Figure 5d (for 5 activity bits) as a Pascal-set type. Sets are stored such that the inclusion or exclusion of aB is represented by the state (1 or 0 respectively) of the Bth activity bit in the activity register. Data and activity masking. To support data and activity masking, without the processing overheads normally incurred with specific mask registers, both the data bus and the activity bus support ternary data. The data bus incorporates a mask field, such that, for each bit of the data register, the data bus can support a 2-bit ternary digit representing one of three values (dX, do, and dl). The digits of the data bus in selected byte fields and those corresponding to the indexed bits of selected serial fields (in byte and bit modes) may be set to any of

Bit model

sf-3

I
AR
=

sf-2

sf-1

set of ( a l , a2, a3, a4, a5) a2 a3 a4 a5

Activity register

a1

Figure 5. Data representation modes in the data redder: wwd (a), byte (b), and bit (c). Activity register storage (d).

the three values. And, all digits in nonselected byte fields and serial fields, plus those digits corresponding to the nonindexed bits of selected serial fields, automatically assume the dX value. However, to economize on ASP chip input ports, designers chose not to allow the dX value in word mode. Similarly, the activity bus supports 2-bit ternary digits such that its Bth activity digit can represent the presence or absence of aB or a masked aB in the activity register. Basic APE operations. APES support four basic operations, match, add, read, and write. Examples of each in pseudo-Pascal statements appear in the accompanying box. In a match operation the M and D tags become true in matching APEs and false in mismatching APEs. In an add operation the M tag and the C flag (in all APES matching the specified activity bits) repre-

Basic APE Operations
Match: the M and D tags become true in matching APEs and false in mismatching APEs, as suggested by the following pseudo-Pascal statements forall APEs do {simultaneouslyin each APE} if D L m a t c h and AR-match then case tagoption of M : the M tag becomes true; MandD : both the M and D tags become true; DaltM : for each ASP segment, the D and M tags become true starting (from the left end of the segment) with D end

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ASP
sent the sum and carry of a bit-serial addition (or subtraction) operation. During read, ASP updates each digit of the data bus DBfi] to the state of the wire-AND (0’s are “stronger” than 1’s) of the corresponding DRG] bits of all activated APEs and their activity registers can be updated. During a write operation ASP updates the data register and the activity register in activated APES according to the states of the data bus and the activity bus. Inter-APE communications network. As indicated in Figure 2, each substring supports two styles of interAPE communication, bit-parallel, single-APE communication via the shared data bus and bit-serial, multiple-APE communication via the inter-APE communications network. Although the former can be used to advantage on many occasions, we discuss the latter here. The inter-APE communications network implements a globally controlled and dynamically reconfigurable, tightly coupled APE interconnection strategy. This strategy supports cost-effective emulation of common network topologies (see box on p. 18). Most significantly, the APE interconnection strategy supports simple modular network extension, to enable tailoring of parallel processing power to match user requirements. In contrast to the networks adopted by other parallel computer architectures, we did not design the interAPE communications network primarily for the transfer of actual data between APEs. Instead, and much more simply, we restricted communication to the highspeed transfer of activity signals (or M-tag patterns) between neighboring or selected remote APEs (those matching the selection criteria). Since APES can easily be activated by content addressing and their data content processed in situ, we reduce the time-consuming movement of data to an absolute minimum.

else case tagoption of M : the M tag becomes false; MandD, DaltM : both the M and D tags become false end where DR-match and AR-match are defined as follows. has been initialized as true

For each APE, assuming DR-match

f o r d j in [l ..n] do {simultaneouslyfor each digit} if DBLj] < > dX then D R m a t c h : = D L m a t c h and (DBLj] = DRLj]); AR-match : = ([included AB bits] < = AR) and {set inclusion test} (AR < = ([al,a2,a3,a4,d] - [excluded AB bits])) If any M tag becomes true, as a result of the match operation, then the global Match Reply also becomes true, otherwise MR becomes false. Add: in all APEs matching the specified activity bits, the M tag and C flag represent the sum and carry of a bit-serial addition (or subtraction) operation, as suggested by the following pseudo-Pascal statements, assuming C has been initialized as ‘0’ forall APEs d o {simultaneouslyin each APE} if AR-match then begin M : = notMO < > (M1 < > (C = 1)); if not MO and (M1 or (C = 1)) or (M1 and (C = 1)) then C := 1 else C : = 0 end where, MO and M1 are derived in each APE, for the bits (indexed by j and k) of selected serial-fields, as follows case addend of :MO : = DB(J) = DR[z]; { scalaraddend} scalar vector : MO : = DRC) = 0; {vector addend} M-tag : MO : = not M {vector addend} end; M1: = DR[k] = 1 {vector augend} 16 IEEEMICRO

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In fact, the APE interconnection strategy supports two modes of inter-APE communication: Circuit-switching. Asynchronous, bidirectional, single-bit communication occurs via multiple signal paths, dynamically configured (programmer transparent) to connect APE sources and corresponding APE destinations of high-speed activation signals. Circuit-switching implements a fully connected permutation and broadcast network for APE selection and inter-APE routing functions. Packet-switching. Synchronous, bidirectional, multibit communication via a high-speed bit-serial shift register, routing M-tag patterns along each APE substring for data/message transfer. To preserve continuity at the two ends of the interAPE communications network, the LKL and LKR ports (shown in Figure 2) allow activation or M-bit signals to be injected and sensed by the external ASP

controller. They also act as the left and right neighbors of the leftmost and rightmost APES in the associative string processor. APE block bypassing. Each substring is partitioned into equal-length APE blocks, separated by block links, as indicated in Figure 6 on p. 19. At an abstract level, and assuming a programmable connection between the LKL and LKR ports, the inter-APE communications network can be considered as a hierarchical chordal-ring structure, with the chords bypassing APE blocks (and groups of APE blocks). The network:
Accelerates inter-APE communication signals. APE blocks, not including destination APES are automatically bypassed for both circuit-switched and (if required) packet-switched modes of inter-APE communication and, if appropriate for the former mode, activated in a single step.

where DR(z) indexes a single-bit serial-field of O’s, and for subtraction (i.e., 2’s complement addition), C is initialized as ‘1’ and MO is not complemented. Read: each digit of the data bus DBU] is updated to the state of the wire-AND (i.e., 0’s are “stronger” than 1’s) of the corresponding DRE] bits of all activated APEs, as suggested by the pseudo-Pascal statements f o r d j in (1 ..n] do if DRtil-test then DBU] : = do else DBE] : = d l where DRUl-test, follows {simultaneouslyfor each bit}

assuming it has been initialized as false, is derived as {simultaneouslyin each APE}
: = DRUJ-test

f o r d APEs do if A then DRljJ-test

or (DRU] = 0)

and the Activity Register AR is updated as for write operations. Clearly, it is sensible to activate only one APE per ASP substring for read operations. Write: the Data Register (DR) and Activity Register (AR) are updated in activated APEs according to the states of the data bus and the activity bus as suggested by the following pseudo-Pascal statements f o r d APEs do {simultaneouslyin each APE} if A then begin foralljin[l..n]do {simultaneouslyfor each bit} if DBE] < > dX then DRU] : = DBU]; AR : = AR + [included AB bits] - [excluded AB bits] end {set union and difference)

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ASP Support of Structured Data
We specifically designed the reconfigurable interAPE communications network of the ASP substring to support any data structure with costeffective emulation of common network topologies. Examples of these topologies appear in Figures C through F. an activity bit (for example, al). Similarly, entries can be separated with another activity bit or with L's, if each entry is allocated a segment (see Figure D)

.

Trees
An n-ary tree can be represented in list form, with the head of each sublist being a parent node and the tail comprising the nchild nodes. One or more consecutive APEs represent each node. Sublists may be delimited with an activity bit or with parentheses as:

Arrays
For vectors, data registers store consecutive elements j in consecutive APEs within a segment, with an activity bit or L's, providing local origins for element j indexing. See Figure C1. For matrices, concatenated vectors (segments) separated with an activity bit or L's represent consecutive matrix rows i. L's provide local origins for column j indexing, as indicated in Figure C2. For cubes, hyperspace structures can be represented in a similar manner to that shown for the matrix. For example, the binary ncube (where n = 3) structure could be represented as shown in Figure C3 and navigated with exchange mappings (see address permutations).

(A(BCD)(EF(GHI))) With this representation many subtrees can be navigated and reduced in parallel.

Graphs
Semantic networks may be represented in list form, as indicated earlier for trees. However, for large complex networks, APE data registers can be allocated to nodes, which comprise in-links (lowercase letters), data (uppercase letters), and out-links ) (see Figure E. Users navigate the semantic network by searching for an in-link that has been read from the out-links of the previously matching node. In general, for address permutation networks we try to avoid the actual movement of data between

Tables
The fields F, each being allocated one or more consecutive APES, are ordered and delimited with

F1
L

F2

F3
L

F1

F2

F3
L

F1

F2

F3
L

Figure D. Table example.

L

L

L

L

aAbe bBcd cC"

dD"

eEfg fF"

gGhi hH"

il**

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APE 000

APE 001

APE 010

APE 011

APE 100

APE 101

APE 110

APE 111

APE 000

APE 001

APE 010

APE 011

APE 100

APE 101

APE 110

APE 111

-

~

p

22

(000) (100) (2)

(001) (101) (010)

(110) (011) (111)

APE 000

APE 001

APE 010

APE 011

APE
100

APE 101

APE 110

APE 111

Figure f. Moving data between APES by exchange (l),shuffle (2), and butterfly (3) techniques.

physically addressed APEs in favor of content addressing and activation alternatives. Modifying logical addresses assigned to a field of APE data registers effectively achieves data transfer, for those algorithms requiring association of data with processor location. However, if data movement between physically addressed APES is definitely required, we accomplish it with one or more of the following techniques. Exchange. We achieve a specified mapping with a single shift in each direction along the substring

for a distance that is an appropriate power of 2, as indicated in Figure Fl’s three examples. Shuffle. For N APEs, we achieve the perfect shuffle in log,N steps by pyramidal neighbor exchange, as shown in Figure F2. Butterfly. For NAPES, a single exchange, as indicated in Figure F3, achieves this address permutation. Shifting. As its name suggests, we achieve this address permutation by synchronously shifting (left or right) M-tag patterns between selected

APEs.

Inter-APE communications network

Figure 6. APE black bypassing.
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Provides APE block defect/fault tolerance. APE blocks failing a test routine, either in manufacture or service, switch out of the string, such that defective or faulty blocks are simply bypassed. To provide cost-effective improvement of inter-APE communication speed and defect/fault tolerance, APE block bypassing depends on the implementation. For example, a VLSI ASP may support bypassing of 8-, 64-, 256-APE block groups and entire ASP suband strings. ULSI/WSI ASPS bypassing block groups of 4 and 64 APES and entire branches (ASP substrings) may be specified as design criteria. To avoid loss of computational efficiency, designers chose to make hardware features of the APE blocks, block links, and block bypassing transparent to the ASP programmer.

multiple substrings, under the control of one controller, to form a SIMSIMD (single-instruction control of multiple SIMD modules) configuration, and multiple substrings, each under the control of an independent controller, to form a MIMSIMD (multiple-instruction control of multiple SIMD modules) configuration. Moreover, by feeding LKL and LKR ports to a programmable router (within the ASP controller), users could also construct reconfigurable ASP structures that could adapt dynamically to the changing needs of complex computational tasks. The reconfigurable structures would provide flexible coverage of the wide range of information processing applications already outlined. In operation, the ASP controller executes a sequence of procedures (stored as microprograms) called by an application program running in the host machine. All APES in a substring receive microinstructions that are broadcast on the control bus. In addition to the microprogram unit, the ASP controller also incorporates a scalar data buffer and a scalar processor. In common with typical high-speed microprogramcontrollers, users could implement a general-purpose controller with standard bit-slice microprocessor components on two double-extended Eurocards. This approach could be reduced to one board for simpler controllers. Indeed, in cases where eventual production volume justifies the extra development cost, semicustom VLSI implementation could reduce the controller to a small chip set. Moreover, for some application-specific ASPS, dedicated control logic could be incorporated on the VLSI ASP substring chip. ASP data communications network. The interprocessor communication network usually dominates parallel computer cost and performance. Consequently, the integration of a cost-effective APE interconnection strategy was a major design goal for the ASP system architecture. Investigation of the interprocessor communication requirements for a wide range of parallel algorithms revealed a Zipf-curve relationship between frequency and distance. Short-distance communication is common and long-distance communication is rare. Consequently, the hierarchical interconnection strategy adopted for ASP supports a high degree of parallelism for local communication (within the inter-APE communications network) and progressively lower degrees of parallelism for longer distance communication (within the inter-APE communications and data communications networks). Thus, we do not restrict SIMSIMD and MIMSIMD configurations to the chordal-ring structure of the inter-APE communications network. For example, we could configure the data communications network

ASP segments and segment links. Each substring may be partitioned into programmer-defined segments, separated by segment links, in support of structured data. See box entitled “ASP Support of Structured data.’’ APE block links incorporate bistables, which can be toggled to convert the block links into programmable segment links. The segment links can be opened or closed to prevent or allow the transmission of inter-APE communication signals between adjacent segments. Thus, each segment comprises a span of contiguous APE blocks, with internal block links closed and end block links converted to segment links. Users can create variable-length segments by writing segment links corresponding to the K t a g s at the ends of APE blocks. Alternatively, they can create equallength segments, comprising power-of-2 APES, with a special command. ASP data buffer. Each ADB module provides data block storage immediately before and after processing within its local substring as shown in Figure 1. In addition to data storage each ADB module incorporates bit-parallel primary and secondary data exchangers (PDX and SDX) similar to those shown for the vector data buffer in Figure 2. In operation the PDX of each ADB module complements the SDX of its ASP substring. The corresponding SDX in each ADB module complements the data interface (DI) and the SDX of other ADB modules via the data communication network. Consequently, in contrast to inter-APE communication within each substring, the ADB modules allow data communication between substrings to be fully overlapped with substring processing. This feature avoids data transfer overheads. ASP controller. With appropriate management of the LKL and LKR ports of multiple ASP substrings within the ASP controller, we achieve two different configurations:
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ASP Operations
registers of all APES to support appropriate
Value-X

I

Va1ue-Y

I

Value-Z

1

where <scalar-vector match condition> tag <tag option>; activate <activation option> do <scalar-vector or vector-vector operation>

Figure H. ASP operation statement

e.g.

for j : = Is-bit to ms-bit do
begin where (DR.field-1 = Value-X) and (a1 in AR) and not (a3 in AR) tag M; activate M-tagged-WEs do begin DR.field-4[j] := Value-Y[j] o DR.field-3[j]; DR.field-3IjI := DR.field-l[j] o DR.field-Zlj] end end

{S-V) {V-V)

~~

Figure 1. Bit&allword-parallel

operations.

shown in Figure 1 to implement an alternative network topology (cross-bar, mesh, torus, shuffle, exchange, butterfly, or binary n-cube). In summary, to optimize cost-effectiveness and application flexibility, ASP incorporates two levels of interprocessor communication. The lower level provides low-cost implementation of large-scale, fine-grain parallelism, and the upper level minimizes (what would have been a high) implementation cost with smallscale, medium-grain parallelism. In addition, a particular performance advantage of this two-level interconnection strategy is that upper-level communications can be fully overlapped with substring processing. To

illustrate the functionality of the architecture we’ve just described, see ASP operations box.

ASP software
The degree of programmability and associated software complexity are key issues for general-purpose parallel computer design. Unfortunately, the history of parallel algorithm development reveals a profoundly steep learning curve, with much evidence of poor exploitation of natural parallelism and cost-ineffective use of applied parallelism. The height of the learning
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ASP

(1)

where DR.field-1 = value-X tag M; activate M-tagged-WEs do begin DR.field-4 := Value-Z; AR := AR + [all - [a31 end

{byte mode only} {byte mode only}
{set union and difference}

e.g.

or bit-parall.el vector-vector addition of WEs marked with activity bit a4, assuming the prior execution of where a4 in AR tag M; activate M-tagged-APES

do C := 0

where (DR[j] = 0) and (DR[k) = 0) and (a4 in AR) tag MandD; where (DR[j] = 1) and (DR[k] = 1) and (a4 in AR) tag M; do C := 1; activate left-substrings-of-M-tagged-APES where a4 in AR tag M; activate M-tagged-APES do DR[r] := DR[j] + DR[k]

(2)

where the variables r, j and k support word-indexing.

Figure 1. Scalar-vector matching and assignment operations (1); vector-vector arithmetic, relational and logical operations (2).

Bit-parallelI ord-parallel w
ASP executes scalar-vector and vector-vector operations in bit-parallel modes, as outlined in Figures 51 and 52. Assuming our data register format, ASP supports bit-parallel/word-parallel, scalar-vector matching and assignment operations of the type seen in Figure J1. Assuming that R-bit data registers of a group of P

contiguous APES are allocated to store R F b i t data words, ASP also supports bit-parallel/ word-parallel vector-vector arithmetic, relational, and logical operations. See Figure 52. Note that in this operating mode we configure an N-APE ASP as N/P P-bit processors, each supported by R P-bit registers. For example, the 256-APE VLSI chip shown in Figure 9 could support 32 8-bit (or sixteen 16-bit or eight 32-bit or four &bit) microprocessors, each with 32 general-purpose registers in this mode.

curve may span as much as two to three orders of magnitude in performance. The solution to this problem should be found in a high-level parallel programming language that offers simple expression of natural parallelism and flexible control of applied parallelism. But, as yet, no widely accepted such parallel programming language exists. Experimenting with existing declarative languages and extending existing procedural languages with parallel processing constructs are unlikely to promote efficient parallel algorithms. Worse still, these languages do not encourage programmers to climb the learning curve and improve parallel processing performance. Indeed, algorithm performance benchmarks, published by parallel computer vendors offering such language extensions, are normally based on assembly-level coding.
22 IEEEMICRO

Moreover, programmers are very reluctant to change their working environments. Indeed, the cultural change to parallel processing is traumatic enough, without complicating the issue by enforcing adoption of an alien programming language and (possibly) an unfamiliar operating system, not to mention the concomitant loss of access to existing software. Consequently, the pragmatic approach adopted for ASP accepts that parallel computer users are best served with their familiar (sequential) software development systems. Users can write ASP application programs entirely in a familiar block-structured, high-level language (Pascal, Modula-2, C, or Ada) under a familiar operating system (Unix, VMS, or MS-DOS). Such programs include calls to external precompiled ASP algorithms and procedures, written and progressivelyrefined

I

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(in the same language) by experts, with an intimate knowledge of the ASP architecture, using a set of builtin function and procedure primitives. Thus, the average ASP application programmer/user does not face the full complexity of parallel algorithm development. The user has the much less-demanding task of selecting and interfacing appropriate code from the hierarchically organized ASP algorithm and procedure library. Only occasionally must programmers resort to the creation of such code. Nevertheless, we are actively investigating parallel constructs for ASP programming. I offer the syntax definitions in Figure 7, written in EBNF (extended Backus-Naur formalism) and the example procedures in Figure 8 in an attempt to explain the nature of ASP programs. ASP procedure examples. The first example of an ASP procedure marks the maximum and minimum values in the data field [Is-bit ...ms-bit] of a subset of positive (binary) integers (already marked with activity bit a4) with activity bits a1 and a2. See Figure 8a. The second example procedure in Figure 8b marks the first and last characters of all words (text strings delimited at both ends with spaces) that match an ncharacter word with activity bits a1 and a2 respectively.

Moreover, ASP is highly amenable to defect/fault tolerance, owing to its construction from a large number of identical APES, lack of location-dependent addressing and simple inter-APE interconnection. Consequently, as reducing feature sizes and increasing chip sizes drive VLSI chip fabrication technology toward the prospect of ULSI chips and WSI devices, the ASP architecture offers consistency and becomes increasingly more cost-effective. Pioneering investigations. In the early seventies Brunel University developed two experimental ASP prototypes. The first (funded by the United Kingdom Department of Industry) was based on LSI associative memory chips, designed by the author and fabricated by GEC-Marconi. We based the second (funded by the UK Science and Engineering Research Council) on a TTL (transistor-transistor logic) emulation of an LSI ASP chip design. Both prototypes demonstrated the architectural principles and low-level software and stimulated interest in the application potential of ASP. The ASP chip development program at Brunel University from 1976 until 1981 included the design at the university and the fabrication at Plessey of two LSI ASP test chips. The project demonstrated the feasibility of microelectronic implementation of the architecture. In addition, a series of research contracts, funded by British Aerospace in 1978 strongly influenced ASP systems and software development. The projects investigated the application of ASP to real-time image processing tasks.
VLSI ASP chips. Since 1981 a three-phase program to develop VLSI ASP chips has been running at Brunel University.

Development program
As mentioned earlier, the ASP concept is particularly well matched to the exciting opportunities and exacting constraints of VLSI chip fabrication. Reasons include the high APE packing density, the highly compact interAPE communications network, and, especially, the independence of I/O requirement from string length. (Compare the linear ASP with a two-dimensional array in which the 110 requirement grows as the square root of the array size.)

Phase I , experimental prototyping. Complementary SCAPE and Script projects ran from 1981 to 1987. Their objectives were to develop VLSI ASP chips that

statement = Pascal-statement

ASP-construct.

ASP-construct = tag-statement ";" {activation-statement}. tag-statement = ifany-statement ifany-statement
=

where-statement.

"ifany" tag-function "then" statement ["else" statement]. "where" tag-function. "tag" tag-option.

where-statement tag-function

=

= match-condition
=

act ivat ion-statement

"activate" act ivat ion-opt ion "do" APE-operat ion.

Figure 7. Syntax definition in ASP parallel constructs.
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ASP

type nrange

=

1..n;

ASPgrocedure W I N (Is-bit,ms-bit:nrange); var j : integer; begin {MAXMIN) where a4 in AR tag M; {set union) activate M-tagged-APES do AR := AR + jal;2!; for j := ms-bit downto Is-bit do begin ifany (DR[j) = 1) a i (a1 in AR) tag M rd then begin where (DR[j] = 0) and (a1 in AR) tag M; activate M-tagged-APES do AR := AR - [all {set difference} end ifany (DR[j] = 0 ) and (a2 in AR) tag M then begin where (DR[j] = 1) and (a2 in AR) tag M; activate M-tagged-APES do AR := AR [a21 {set difference} end end end {MAXMIN)

-

ASPgrocedure FIND-WORDS (n:integer;word:string); var i : integer; match : boolean; begin {FIND-WORDS) i := 1; match := true; where I] <= AR tag M; activate M-tagged-APES do AR := [I; where DR = ' ' tag Man&; activate right-neighbours-of-M-tagged-APES do AR := AR + [al,a2]; while (i <= n) and match do begin ifany (DR = wordli]) and (a2 in AR) t:?q Ir. then begin activate all-APES do AR := AR - [a2]; activate right-neighbours-of-M-tagged-APES AR := AR + [a21 end else match := false; i:=i+1 end; if match then begin where (DR = ' ' ) and (a2 in AR) tag M; activate left-substrings-of-M-tagged-APES do

{set union}

{set difference} do {set union}

AR := AR + [a3]; {set union) where (DR = wordll]) and ([al,a3] in AR) tag M; activate all-APES do AR := AR - [al,a3]; {set difference) activate M-tagged-APES do AR := AR + [all {set union} where a2 in AR tag U; activate all-APEs do AR := AR - [a2]; {set difference) activate left-neighbours-of-M_tagged-APEs do AR := AR + [ l d {set union) end else write ('match fails')

end {FIND-WORDS}

Figure 8. Example ASP pmcedum: marking the maximum and minimum dues in the data field (a); marking the first and lost characters of all matching wards (b).
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Plans call for construction of application-specific and generalpurpose chips for research and commercial exploitation.
would demonstrate the applicability of the ASP architecture to numerical (image processing) and nonnumerical (text-based symbolic processing) applications and assess their cost-effectiveness. In 1986 Plessey fabricated the first samples of the 68-pin SCAPE (single-chip array processing element) chip. The chip is a 256-APE (32-bit data and five activity bits) VLSI ASP (funded by the UK Ministry of Defence from December 1982) in a 2pm complementary metal-oxide semiconductor (CMOS) process with two-layer The SCAPE chip appears in Figure 9. A two-year research contract funded by UK’s Alvey (Man Machine Interface) initiative involved collaboration with Quantel UK and the University of Bristol to investigate the design and evaluation of SCAPE-based image processing equipment. Another two-year Alvey VLSI contract, starting November 1984 and involving Plessey, detailed a design requirement analysis and architectural specification for the Script chip. We based the chip on design and performance data derived from the SCAPE project. Presently, Brunel University is investigating the design and evaluation of Script-based systems as part of the Scantrax (a back-end processor for relational database management and information retrieval) project.
Phase 2, design consolidation. Since 1987 we based ASP implementation activity on the development of a cell-based design methodology. The methodology allows the VLSI chip designer to select fully engineered, exactly butting, CMOS layout cells from the ASP cell library and compose specific layout blocks for full-custom VLSI chips. Both Brunel University and Aspex Microsystems staffs pursue such design consolidation in complementary tasks. The former activity investigates new cells and cell variants in research projects, and the latter provides the engineering development required to enable commercial VLSI ASP chips to be based on library cells. To date, Phase 2 has involved the development of four VLSI ASP test chips, fabricated through the silicon foundry services of the UK’s MCE Company

Figure 9. Photomicrograph of the VLSl ASP (WPE) chip.

and a 64-APE (32-bit data and five activity bits) VLSI chip. Currently, Plessey is fabricating the latter (in 2pm CMOS with two-layer metal). Based on new cells and incorporating design improvements, this SCAPElike VLSI chip is intended for ASP demonstrator construction.
Phase 3, product development. Following establishment of a comprehensive cell library, plans call for phase 3 to develop both application-specific and general-purpose VLSI chips for ASP construction for both university research and commercial exploitation. Prominent among such chips are 256-APE and 1,024-APE VLSI chips being developed by Aspex Microsystems for fabrication in 1989 and 1990.

ULSI and WSI devices. Since the cost-performance potential of the ASP architecture improves with increasing string length, demonstration of the advantages of SCAPE-based image processing modules stimulated us to further research leading toward more improvements in cost-effectiveness. Moreover, since the ASP is so highly amenable to defect tolerance that chip area ceases to be a limiting factor, ULSI and WSI ASP devices become natural targets. An important advantage gained by significantly increasing chip size is that we can also integrate much of the ASP controller and data communications network on the same chip. Indeed, in contrast to VLSI building blocks for the implementation of substrings (see Figures 2 and 9), ULSI and WSI devices implement an entire ASP system, as shown in Figure 1, on a single
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\

0ASP
ADB Communication and control Wafer interface
I I
I I

Communication and control

Figure 10. ULSl ASP chips.

Figure 11. WSI ASP device.

silicon die. A single die offers major savings in size, weight, and cost together with increased reliability and ease of maintenance. ULSI and WSI devices, comprising 2,048 and 8,192 APEs, as shown in Figures 10 and 11, are being investigated in the WASP (WSI Associative String Processor) project at Brunel University. The project includes the fabrication and evaluation of defect/fault-tolerant test chips and ULSI/WSI ASP technology demonstrators. It has been funded since 1985 under a UK Alvey (VLSI) contract and involves Plessey, GEC, ICL, and Middlesex Polytechnic. In a separate project, Aspex Microsystems under a US Office of Naval Research contract is developing a WASP application demonstrator for iconic to symbolic image processing for fabrication in 1990.

0

8 2

103-

WSI ASP devices

VLSI ASP chips

ASP performance forecasts
To provide a simple indication of ASP performance, we designed VLSI/ULSI/WSI ASP chips (with 2pm CMOS fabrication technology) to allow each step of bit-serial and bit-parallel operations to be completed in 100 nanoseconds. Consequently, we can estimate the
26 IEEEMICRO

io0

io1

io*

103 io4 Number of APEs

105

io6

Figure 12. ASP performance estimation. MOPS = million o e t m per second. p ni o

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limit of performance of an N-APE ASP approximately as follows: 10 x N MOPS Performance = No. steps per operation Based on this expression, Figure 12 displays the potential performance of VLSI/ULSI ASP chips and WSI ASP devices.

he Associative String Processor is a highly versatile, parallel processing,computational architecture with the potential to achieve step functions in cost-performance over a wide range of information

T

processing tasks. Indeed, ASP hardware and software modules provide the core technology for the construction of cost-effective, general-purpose and applicationspecific computer workstations designed for the end user. Having described its architectural philosophy, structural organization, operational principles, and microelectronic implementation, I review the ASP in terms of the desirable features for fifth-generation computer systems shown in Table 2. In terms of cost-effectiveness, application studies and benchmark evaluations demonstrate that ASP can match and often improve on the performance figures of contemporary parallel computers. And, consequently, the competitive edge becomes that of implementation cost.

Table 2. ASP features applicable to fifth-generation computing systems.

Feature Application flexibility

Description

A a fully programmable parallel processor with a reconfgurable s
interprocessor communication network, ASP provides flexible support for structured data processing thereby amortizing procurement costs over a wide range of both numerical and nonnumerical information processing applications. By mapping all data to intermediate string-processing form, which can be accessed associatively and is supported by a reconfigurable interprocessor communication network, ASP provides simple support of data-level application parallelism (concurrency occurring naturally in structured data and in the algorithmic requirement) and simple control of process and instructionlevel parallelism. By enabling close matching between the applied parallelism of its architecture and the natural parallelism of applications with the interprocessor communication network, and by reducing sequential processing overheads with elimination of redundant processing, processor addressing, and unnecessary data movement, ASP m a x i m i computational efficiency with content addressing and in-situ processing. As a homogeneous parallel computer, ASP allows scaling of processing power with simple modular adjustment of string length to match user performance requirements. By exploiting the latest advances in the VLSI-to-ULSI-to-WSI technological trend and high-density system assembly techniques, users can implement ASP in a very compact form. Sne only active processors dissipate and redundant processing has been ic eliminated, state-of-the-art microelectronic implementation allows ASP to be designed for low power consumption. As a fault-tolerant pardel architecture exploiting microelectronics technology, ASP offexs high reliability and ease of maintenance. Owing to its simple homogeneous string structure, ASP benefits from the inevitable improvement in microelectronics technology (increasing chip size and reducing feature size) without architectural or software modification.
October 1988
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Operational simplicity

Computational efficiency

Architectural extensibility Size and weight Power requirement System reliability Technology independence

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ASP
In contrast to its contemporaries, we specifically developed ASP as a silicon-efficient parallel architecture. We achieved cost reductions by maximizing processor packing density, incorporating the interprocessor communications network on chip, and using defect/ tolerant circuit design. With 9,472 bits of content-addressable storage on a VLSI chip (with a 2pm feature size), Figure 9 demonstrates that the processor packing density ASP achieves is not too far behind that achievable with static RAM chips. Since system designers seem not to be concerned that all (but one) RAM storage locations are idle at any given instant, whereas many (if not all) ASP processors can be simultaneously active, it can be claimed that ASP has achieved the goal of compensating for inevitable processor redundancy with implementation cost reduction. The curves of Figure 12 indicate potential ASP costperformance. Assume that VLSI chips could be produced (in volume) for less than $100 each, that the chips dominate system implementation costs (an unlikely event, but prediction of system implementation costs are beyond the scope of this article). Allow (therefore) an arbitrary factor of 10 for a contingency/profit margin. Also estimate an order-of-magnitude improvement with WSI ASP devices. With these assumptions the comparative cost-performance curves in Figure 13 indicate the potential of 100 MOPS/ $l,OOO and 1,OOO MOPS/$l,OOO for VLSI- and WSIbased ASPS. For a more objective assessment of ASP
IU

cost-effectiveness, consider the following comparison of ASP with Thinking Machine’s CM-1 (the Connection Machine).g The 16-processor-element CM-1 processor chip and the 256-APE SCAPE chip share a common 68-pin package. Therefore, it seems reasonable to assume that a CM-1 printed circuit board (accommodating 32 processor chips, supporting RAM, “glue” logic) could and implement 8,192 APES, supporting ASP data buffer and glue logic. Moreover, our detailed design studies show that a SIMSIMD ASP controller and data communications network for an ASP system, as shown in Figure 1, would only require one such board. The CM-1 requires at least an additional 12 boards (assumed, since the processor boards account for more than 90 percent of CM-1 circuitry9) for interprocessor communication, control, and input-output interfacing. In summary, a 64K-APE VLSI ASP system would require only nine boards and an equivalent WSI ASP would require only eight wafers. Compare this with the 140 boards required for the 64K-processor CM-1. Moreover, with a one-square-centimeter area, the CM-1 chip costs approximately twice as much as the 75-square-millimeter SCAPE chip, 5,6 for typical VLSI foundry fabrication defect densities. For a 32-bit addition, the peak performance of a 64K-APE ASP would be around 20 gigaoperations per second, compared with only one GOPS for the CM-1. The CM-1 dissipates 12 kW of power; the VLSI and WSI + ASPS would dissipate less than 300W and 1OOW. $

1

- 1000
32-bit add

MOPS/$K

106

- 100 MOPS/$K

1 o5

-

10 MOPS/$K

1o4

-

1 MOPS/$K

a cn
0

I

1o3

-

0.1 MOPS/$K

102

I

n MicroVAX II, VAX 8600, Cray XMPI14
Butterfly, IPSC (hypercube), AMT DAP, ConnectionMachine

10’

I
100
101 102 103

riv

VLSI parallelprocessors

LLY ULSINVSI parallelprocessors

lo4 Dollars

105

106

1

Figure 13. ASP cost-effectiveness. MOPS = million operations per second.
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Acknowledgments
I gratefully acknowledge the enthusiastic contributions t o ASP-based projects f r o m past and present members o f the Computer Architecture Group and Aspex Microsystems Ltd. a t Brunel University, t h e support o f the UK Alvey initiative, a n d U S Office of Naval Research funding.

References
1. R.M. Lea, “Associative Processing,” Advanced Digital

2.

3.

4.

5.

Information Systems, I. Aleksander, ed., Prentice-Hall, New York, 1985, pp. 531-575. R.M. Lea, “VLSI and WSI Associative String Processors for Cost-effective Parallel Processing,” The Computer Journal, Vol. 29, No. 6, 1986, pp. 486-494. R.M. Lea, “VLSI and WSI Associative String Processors for Structured Data Processing,” IEE Proc. Comput. and Digital Tech., London, Vol. 133, Pt. E3, 1986, pp. 1 53- 162. R.M. Lea, “The ASP, a Fault-Tolerant VLSI/ULSI/ WSI Associative String Processor for Cost-Effective Systolic Processing,” Proc. IEEE Int ’I. Conf. Systolic Arrays, K. Bromley, S.Y. Kung, and E. Swartzlander, eds., CS Press, Los Alamitos, Calif., 1988, pp. 515-524. R.M. Lea, “SCAPE: a Single-Chip Array Processing Element for Signal and Image Processing,” IEE Proc., Vol. 133, Pt. E3, 1986, pp. 145-151.

R. M. Lea is the chief executive of Aspex Microsystems Ltd. and professor of microelectronics in the Electrical Engineering and Electronics Department of Brunel University. He specializes in parallel computer and VLSI chip architecture. In 1971 he began the Brunel Computer Architecture Research Group after recognizing the potential emerging from his GEC-Marconi associative memory project. While maintaining close links with industry, he has directed over 250 manyears of research in ASP systems for computer vision and symbolic-processing applications. Lea founded Aspex Microsystems Ltd. in 1986 as a professional division of his research group to exploit ASP technology. Aspex complements academic research with industrial development and the ability to trade as an independent company. Lea holds BSc and ARCS degrees from Imperial College and the MSc from Chelsea College, both of London University. He is an IEE fellow, and as speaker, chairman, and organizer he has contributed to many international workshops and conferences.

6. I.P. Jalowiecki and R.M. Lea, “A 256-Element Associative Parallel Processor,” ISSCC, 1987, pp. 1%- 197. 7. S.R. Jones et al., “A 9Kbit Associative Memory for Parallel Processing Applications,” IEEE JSSC, Vol. 23, NO. 2, 1988, pp. 543-548.
8. R.M. Lea, “A WSI Image Processing Module, Wafer Scale Integration,” G. Saucier and J. Trilhe, eds., Elsevier Science Publishers B.V. (North-Holland), 1986, pp. 43-58. 9. D. Hillis, The Connection Machine, MIT Press, Cambridge, Mass., 1986.

Questions concerning this article can be addressed to R. M. Lea, Brunel University, Uxbridge, Middlesex UB8 3PH, United Kingdom.

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